التفاصيل البيبلوغرافية
| العنوان: |
23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration scheme |
| المؤلفون: |
Lee, Chang-Kyo, Eom, Yoon-Joo, Park, Jin-Hee, Lee, Junha, Kim, Hye-Ran, Kim, Kihan, Choi, Young, Chang, Ho-Jun, Kim, Jonghyuk, Bang, Jong-Min, Shin, Seungjun, Park, Hanna, Park, Sujin, Choi, Young-Ryeol, Lee, Hoon, Jeon, Kyong-Ho, Lee, Jae-Young, Ahn, Hyo-Joo, Kim, Kyoung-Ho, Kim, Jung-Sik, Chang, Soobong, Hwang, Hyong-Ryol, Kim, Duyeul, Yoon, Yoon-Hwan, Hyun, Seok-Hun, Park, Joon-Young, Song, Yoon-Gyu, Park, Youn-Sik, Kwon, Hyuck-Joon, Bae, Seung-Jun, Oh, Tae-Young, Song, In-Dal, Bae, Yong-Cheol, Choi, Jung-Hwan, Park, Kwang-Il, Jang, Seong-Jin, Jin, Gyo-Young |
| المصدر: |
2017 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2017 IEEE International. :390-391 Feb, 2017 |
| Relation: |
2017 IEEE International Solid- State Circuits Conference - (ISSCC) |
| قاعدة البيانات: |
IEEE Xplore Digital Library |
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