مؤتمر
Lower power Viterbi decoder architecture with a new clock-gating trace-back unit
| العنوان: | Lower power Viterbi decoder architecture with a new clock-gating trace-back unit |
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| المؤلفون: | Je Hyuk Ryu, Sang Cheon Kim, Jun Dong Cho, Hyun Woo Park, Yung Hoon Chang |
| المصدر: | ICVC '99. 6th International Conference on VLSI and CAD (Cat. No.99EX361) VLSI and CAD VLSI and CAD, 1999. ICVC '99. 6th International Conference on. :297-300 1999 |
| Relation: | ICVC'99. 6th International Conference on VLSI and CAD |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 0780357272 9780780357273 |
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| DOI: | 10.1109/ICVC.1999.820910 |