Performance Evaluation Based on Placement Planning of Logic Blocks in FPGA Design

التفاصيل البيبلوغرافية
العنوان: Performance Evaluation Based on Placement Planning of Logic Blocks in FPGA Design
المؤلفون: Joseph, Jasmine, Chalil, Anu
المصدر: 2018 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET) Wireless Communications, Signal Processing and Networking (WiSPNET), 2018 International Conference on. :1-4 Mar, 2018
Relation: 2018 International Conference on Wireless Communications, Signal Processing and Networking (WiSPNET)
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:9781538636244
9781538636237
DOI:10.1109/WiSPNET.2018.8538652