Device layout dimension impact on substrate effective resistivity

التفاصيل البيبلوغرافية
العنوان: Device layout dimension impact on substrate effective resistivity
المؤلفون: Rack, M., Nyssens, L., Raskin, J. -P., Lederer, D., Paganini, A., Shinde, M. B., Beganovic, A.
المصدر: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S) SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2018 IEEE. :1-2 Oct, 2018
Relation: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)
قاعدة البيانات: IEEE Xplore Digital Library
الوصف
ردمك:9781538676271
9781538676264
DOI:10.1109/S3S.2018.8640211