مؤتمر
Power Reduction in Domino Logic Using Clock Gating in 16nm CMOS Technology
| العنوان: | Power Reduction in Domino Logic Using Clock Gating in 16nm CMOS Technology |
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| المؤلفون: | Singhal, Smita, Mehra, Anu, Tripathi, Upendra |
| المصدر: | 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) Signal Processing and Integrated Networks (SPIN), 2019 6th International Conference on. :274-277 Mar, 2019 |
| Relation: | 2019 6th International Conference on Signal Processing and Integrated Networks (SPIN) |
| قاعدة البيانات: | IEEE Xplore Digital Library |
| ردمك: | 9781728113791 9781728113807 |
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| DOI: | 10.1109/SPIN.2019.8711713 |