مؤتمر
Performance Analysis of Adder Architecture using Modified Pass transistor Adiabatic Logic Circuits
| العنوان: | Performance Analysis of Adder Architecture using Modified Pass transistor Adiabatic Logic Circuits |
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| المؤلفون: | Bhuvana, B P, Bhaaskaran, V S Kanchana |
| المصدر: | 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT) Smart Systems and Inventive Technology (ICSSIT), 2019 International Conference on. :1003-1007 Nov, 2019 |
| Relation: | 2019 International Conference on Smart Systems and Inventive Technology (ICSSIT) |
| قاعدة البيانات: | IEEE Xplore Digital Library |
| ردمك: | 9781728121192 9781728121185 |
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| DOI: | 10.1109/ICSSIT46314.2019.8987840 |