التفاصيل البيبلوغرافية
| العنوان: |
Clock Tree Synthesis Techniques for Optimal Power and Timing Convergence in SoC Partitions |
| المؤلفون: |
Vishnu, Priya V, Priyarenjini, A R, Kotha, Naveen |
| المصدر: |
2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) Recent Trends on Electronics, Information, Communication & Technology (RTEICT), 2019 4th International Conference on. :276-280 May, 2019 |
| Relation: |
2019 4th International Conference on Recent Trends on Electronics, Information, Communication & Technology (RTEICT) |
| قاعدة البيانات: |
IEEE Xplore Digital Library |
