دورية أكاديمية
Majority Logic Circuit Minimization Using Node Addition and Removal
| العنوان: | Majority Logic Circuit Minimization Using Node Addition and Removal |
|---|---|
| المؤلفون: | Ko, C., Lin, C., Chen, Y., Wang, C. |
| المصدر: | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on. 41(3):642-655 Mar, 2022 |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | تدمد: | 02780070 19374151 |
|---|---|
| DOI: | 10.1109/TCAD.2021.3060648 |