25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM

التفاصيل البيبلوغرافية
العنوان:	25.2 A 16Gb Sub-1V 7.14Gb/s/pin LPDDR5 SDRAM Applying a Mosaic Architecture with a Short-Feedback 1-Tap DFE, an FSS Bus with Low-Level Swing and an Adaptively Controlled Body Biasing in a 3rd-Generation 10nm DRAM
المؤلفون:	Kim, Yong-Hun, Kim, Hyung-Jin, Choi, Jaemin, Ahn, Min-Su, Lee, Dongkeon, Cho, Seung-Hyun, Park, Dong-Yeon, Park, Young-Jae, Jang, Min-Soo, Kim, Yong-Jun, Choi, Jinyong, Yoon, Sung-Woo, Jung, Jae-Woo, Park, Jae-Koo, Lee, Jae-Woo, Kwon, Dae-Hyun, Cha, Hyung-Seok, Cho, Si-Hyeong, Kim, Seong-Hoon, You, Jihwa, Kim, Kyoung-Ho, Kim, Dae-Hyun, Kim, Byung-Cheol, Kim, Young-Kwan, Kim, Jun-Ho, Choi, Seouk-Kyu, Kim, Chan-Young, Na, Byong-Wook, Choi, Hye-In, Oh, Reum, Ihm, Jeong-Don, Bae, Seung-Jun, Kim, Nam Sung, Lee, Jung-Bae
المصدر:	2021 IEEE International Solid-State Circuits Conference (ISSCC) Solid-State Circuits Conference (ISSCC), 2021 IEEE International. 64:346-348 Feb, 2021
Relation:	2021 IEEE International Solid-State Circuits Conference (ISSCC)
قاعدة البيانات:	IEEE Xplore Digital Library