التفاصيل البيبلوغرافية
| العنوان: |
Virtex 7 FPGA Implementation of 256 Bit Key AES Algorithm with Key Schedule and Sub Bytes Block Optimization |
| المؤلفون: |
Gunasekaran, Mahendrakumar, Rahul, Kumar, Yachareni, Santosh |
| المصدر: |
2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS) IOT, Electronics and Mechatronics Conference (IEMTRONICS), 2021 IEEE International. :1-6 Apr, 2021 |
| Relation: |
2021 IEEE International IOT, Electronics and Mechatronics Conference (IEMTRONICS) |
| قاعدة البيانات: |
IEEE Xplore Digital Library |
