مؤتمر
An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V
| العنوان: | An enhanced 130 nm generation logic technology featuring 60 nm transistors optimized for high performance and low power at 0.7 - 1.4 V |
|---|---|
| المؤلفون: | Thompson, S., Alavi, M., Arghavani, R., Brand, A., Bigwood, R., Brandenburg, J., Crew, B., Dubin, V., Hussein, M., Jacob, P., Kenyon, C., Lee, E., Mcintyre, B., Ma, Z., Moon, P., Nguyen, P., Prince, M., Schweinfurth, R., Sivakumar, S., Smith, P., Stettler, M., Tyagi, S., Wei, M., Xu, J., Yang, S., Bohr, M. |
| المصدر: | International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224) Electron devices meeting 2001 Electron Devices Meeting, 2001. IEDM '01. Technical Digest. International. :11.6.1-11.6.4 2001 |
| Relation: | International Electron Devices Meeting. Technical Digest |
| قاعدة البيانات: | IEEE Xplore Digital Library |
Full Text Finder | ردمك: | 0780370503 9780780370500 |
|---|---|
| DOI: | 10.1109/IEDM.2001.979479 |