Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails

التفاصيل البيبلوغرافية
العنوان:	Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails
المؤلفون:	Veloso, A., Jourdain, A., Radisic, D., Chen, R., Arutchelvan, G., O'Sullivan, B., Arimura, H., Stucchi, M., Keersgieter, A. De, Hosseini, M., Hopf, T., D'Have, K., Wang, S., Dupuy, E., Mannaert, G., Vandersmissen, K., Iacovo, S., Marien, P., Choudhury, S., Schleicher, F., Sebaai, F., Oniki, Y., Zhou, X., Gupta, A., Schram, T., Briggs, B., Lorant, C., Rosseel, E., Hikavyy, A., Loo, R., Geypen, J., Batuk, D., Martinez, G. T., Soulie, J. P., Devriendt, K., Chan, B. T., Demuynck, S., Hiblot, G., der Plas, G. Van, Ryckaert, J., Beyer, G., Litta, E. Dentoni, Beyne, E., Horiguchi, N.
المصدر:	2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) VLSI Technology and Circuits (VLSI Technology and Circuits), 2022 IEEE Symposium on. :284-285 Jun, 2022
Relation:	2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
قاعدة البيانات:	IEEE Xplore Digital Library