High-Level Synthesis for SiLago : Advances in Optimization of High-Level Synthesis Tool and Neural Network Algorithms

التفاصيل البيبلوغرافية
العنوان:	High-Level Synthesis for SiLago : Advances in Optimization of High-Level Synthesis Tool and Neural Network Algorithms
بيانات النشر:	KTH, Elektronik och inbyggda system Sweden 2022
تفاصيل مُضافة:	Yang, Yu
نوع الوثيقة:	Electronic Resource
مستخلص:	Embedded hardware designs and their automation improve energy and engineering efficiency. However, these two goals are often contradictory. The attempts to improve energy efficiency often come at the cost of engineering efficiency and vice-versa. High-level synthesis (HLS) is a good example of this challenge. It has been researched for more than three decades. Nevertheless, it has not become a mainstream design flow component concerning custom hardware synthesis due to the big efficiency gap between the HLS-generated hardware design and the manual RTL design. This thesis attempts to address the HLS challenge. We divide the research challenge of improving state-of-the-art HLS into three components: 1) the hardware architecture and its underlying VLSI design style, 2) the design automation algorithms and data structures, and 3) the optimization of the algorithm to be mapped. The SiLago hardware platform has been reported as a prominent hardware architecture that can deliver ASIC-like efficiency and could be an ideal HLS hardware platform. It has the following features: 1) SiLago embodies parallel distributed two-level control. 2) SiLago blocks are hardened blocks that can create valid VLSI designs by abutment without involving logic or physical synthesis. Consequently, when targeting the SiLago hardware platform, the SiLago HLS tool generates not a single controller but multiple collaborative controllers, each of which is a hierarchy of two levels. The distributed two-level control scheme poses unique challenges in synchronization and scheduling tasks. Unique data structures and instruction scheduling models are developed for the SiLago HLS tool to support the distributed two-level control scheme. The SiLago HLS tool also generates a valid GDSII macro whose average energy, area, and performance are not estimated but known with post-layout accuracy thanks to the predictable SiLago hardware blocks. Moreover, the SiLago HLS tool is not intended for the end-user. It is de Automatiseringen av inbyggda system ökar ingenjörers produktivitet och minskar systemens energiförbrukning. Målen är ofta motstridiga då högre ingenjörsproduktivitet sker på bekostnad av energiförbrukning och vice versa. Högnivåsyntes (high-level synthesis, HLS) exemplifierar dilemmat. Trots att det forskats i mer än tre decennier på HLS har inte designmetodiken blivit mainstream inom elektronikdesign på grund av det stora effektivitetsgapet mellan den HLS-genererade och den manuellt skapade RTL-designen. Avhandlingen handlar om detta dilemma. Forskningsutmaningarna kring att förbättra HLS avhandlar vi i tre delar: 1) hårdvaruarkitektur och underliggande VLSI-designmetodik, 2) elektronikdesignens algoritmer och datastruktuer och 3) optimering av den algoritm som ska implementeras. SiLago-plattformen har visats vara en framstående hårdvaruarkitektur som kan uppnå ASIC-liknande prestanda samtidigt som den är en idealisk för HLS. Plattformen har följande egenskaper: 1) SiLago förkroppsligar den parallella distribuerade två-nivåskontrollparadigmen, 2) SiLago-komponenter är försyntetiserade med vilka funktionella VLSI-designer kan skapas genom hopfogning utan ytterligare logisk eller fysisk syntes. Därför skapar inte SiLagos HLS-verktyg en enda controller utan flera stycken samverkande controllers. Var och en av dessa består av en tvånivåshierarki. Detta medför unika synkroniserings- och schemaläggningsutmaningar. Unika datastrukturer och schemaläggningsmodeller har utvecklats för SiLago HLS för att stödja denna två-nivåskontrollparadigm. Därutöver skapar SiLagos HLS-verktyg GDSII-makron vars genomsnittliga energiförbrukning, yta och prestanda inte uppskattas utan bestäms med post-layout precision tack vare SiLagos försyntetiserade komponenter. Målgruppen för SiLagos HLS-verktyg är inte slutanvändare utan utvecklare som utvecklar algoritmbibliotek som sedan används av SiLagos applikationssyntesverktyg (application level synthesis, ALS). Applikationen ses som en hierarki QC 20220914
مصطلحات الفهرس:	Electronic Design Automation (EDA), Computer Aided Design (CAD), Algorithm-level Synthesis, SiLago, Optimization Techniques, Neural Network, Embedded Systems, Inbäddad systemteknik, Doctoral thesis, comprehensive summary, info:eu-repo/semantics/doctoralThesis, text
URL:	http://urn.kb.se/resolve?urn=urn:nbn:se:kth:diva-317555 TRITA-EECS-AVL ; 2022:48
الإتاحة:	Open access content. Open access content info:eu-repo/semantics/openAccess
ملاحظة:	application/pdf English
أرقام أخرى:	UPE oai:DiVA.org:kth-317555 0000-0003-2396-3590 urn:isbn:978-91-8040-300-9 1372248835
المصدر المساهم:	UPPSALA UNIV LIBR From OAIster®, provided by the OCLC Cooperative.
رقم الأكسشن:	edsoai.on1372248835
قاعدة البيانات:	OAIster

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