Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits

التفاصيل البيبلوغرافية
العنوان:	Body Bias Generator for Leakage Power Reduction of Low-Voltage Digital Logic Circuits
المؤلفون:	Jeong, Ji-Yong^Aff19, Kim, Gil-Su^Aff19, Son, Jong-Pil^Aff19, Rim, Woo-Jin^Aff19, Kim, Soo-Won^Aff19
المساهمون:	Hutchison, David, editor^Aff1, Kanade, Takeo, editor^Aff2, Kittler, Josef, editor^Aff3, Kleinberg, Jon M., editor^Aff4, Mattern, Friedemann, editor^Aff5, Mitchell, John C., editor^Aff6, Naor, Moni, editor^Aff7, Nierstrasz, Oscar, editor^Aff8, Pandu Rangan, C., editor^Aff9, Steffen, Bernhard, editor^Aff10, Sudan, Madhu, editor^Aff11, Terzopoulos, Demetri, editor^Aff12, Tygar, Dough, editor^Aff13, Vardi, Moshe Y., editor^Aff14, Weikum, Gerhard, editor^Aff15, Vounckx, Johan, editor^Aff16, Azemard, Nadine, editor^Aff17, Maurine, Philippe, editor^Aff18
المصدر:	Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation : 16th International Workshop, PATMOS 2006, Montpellier, France, September 13-15, 2006. Proceedings. 4148:350-359
قاعدة البيانات:	Springer Nature eBooks

الوصف
ردمك:	9783540390947 9783540390978
DOI:	10.1007/11847083_34